1. Field of the Invention
The present invention relates to a semiconductor memory device that performs a memory-cell program operation and a verify operation for verifying a memory-cell program state and to a control method for the program and verify operations.
2. Description of the Related Art
By way of an example of conventional semiconductor memory devices, a NOR-type flash memory device and an operation method for the memory device will be described hereinbelow with reference to FIGS. 4 to 6.
FIG. 4 is a circuit diagram showing an example of a major portion configuration of a conventional NOR flash memory device 1. FIG. 5 shows a diagram of a threshold voltage distribution in the NOR flash memory device 1 capable of storing two bits per cell.
Referring to FIG. 4, the NOR flash memory device 1 has a program control circuit 11; a word line voltage generator 12; a main array row decoder 13; a plurality of main cells 14 (only one of which is shown for simplicity); a reference cell row decoder 15; a reference cell RefA of a reference of a referential threshold voltage (minimum set value Vtmin); a reference cell RefB of a referential threshold voltage (maximum set value Vtmax); a determination-dedicated sense amplifier S/A; a main-cell read load 16; a reference-cell dedicated read load 17; a program circuit 18; and a switch devices 16A, 17A, 18A, 19, 20A, and 20B. The plurality of main cells 14 are configured in the form of a flash cell array formed of a plurality of floating-gate transistors.
The program control circuit 11 controls and/or performs processing as described hereunder. In the event of the execution of a verify operation, the program control circuit 11 outputs a verify execution signal VRFY1 to the word line voltage generator 12 and switch devices 16A and 17A. Concurrently, the program control circuit 11 outputs a reference-cell selection signal RSA (or RSB) to the reference cell RefA (or Ref B). Further, for the execution of a program operation, the program control circuit 11 outputs a program execution signal PROG to the word line voltage generator 12 and the switch device 18A.
In more detail, the program control circuit 11 controls and/or performs the processing as described hereunder. In accordance with a verify determination signal VRFY2 received from the sense amplifier S/A, a program pulse is applied from the program circuit 18 to a selected main cell 14, the processing executes a verify operation. Then, the processing determines whether the threshold voltage of the main cell 14 is higher than or equal to the threshold voltage Vtmin of the reference cell RefA. If the processing determines that the threshold voltage of the main cell 14 is lower than the threshold voltage Vtmin, the processing returns to the step of programming (reprogramming). On the other hand, as the determination result, if the threshold voltage is higher than or equal to the threshold voltage Vtmin, the processing determines whether the threshold voltage of the main cell 14 is lower than or equal to the threshold voltage Vtmax of the other reference cell RefB. (In this step, the processing switches from the reference-cell selection signal RSA to the reference-cell selection signal RSB). If the threshold voltage of the main cell 14 is lower than or equal to the threshold voltage Vtmax of the reference cell RefB, the processing executes a normal program termination. On the other hand, if the threshold voltage is not lower than or equal to the threshold voltage Vtmax of the reference cell RefB, the processing executes a forced program termination process (causes program failure).
Upon receipt of the program execution signal PROG from the program control circuit 11, the word line voltage generator 12 outputs a programming voltage the main array row decoder 13 and the reference cell row decoder 15. In addition, upon receipt of the verify execution signal VRFY1 from the program control circuit 11, the word line voltage generator 12 outputs a verify voltage to the main array row decoder 13 and the reference cell row decoder 15.
The main array row decoder 13 decodes an input address signal ADD. Corresponding to a given address, the main array row decoder 13 outputs a verify voltage or a programming voltage to a to-be-selected main array word line, and selects a predetermined main cell 14. Thus, the main array row decoder 13 has not only the function of decoding an address signal, but also a driver function for feeding a word line voltage (i.e., the verify voltage or the programming voltage in the present case) generated in the word line voltage generator 12. Similarly, a column decoder (not shown) decodes an input address signal ADD and outputs a column section signal COL to thereby select a predetermined to-be-selected bit line corresponding to a given address.
The reference cell row decoder 15 is responsible of decoding an input reference address signal ADDREF to output a verify voltage to a reference-cell dedicated word line and then to select a predetermined reference cell RefA or reference cell RefB. Thus, the reference cell row decoder 15 has not only the function of decoding the reference address signal ADDREF, but also a driver function for feeding a word line voltage (i.e., the verify voltage or the programming voltage in the present case) generated in the word line voltage generator 12.
For execution of the verify operation, the sense amplifier S/A performs a comparison and a determination whether the threshold voltage of the selected main cell 14 is higher than or equal to the threshold voltage Vtmin of the reference cell RefA. Then, the sense amplifier S/A outputs the verify determination signal VRFY2 as a resultant signal to the program control circuit 11.
While only the two reference cells RefA and RefB are shown in FIG. 4, other reference cells need to be provided corresponding to other memory states. In addition, the configuration shown in FIG. 4 uses the reference cell row decoder 15 to individually select the reference cells RefA and RefB. However, since columns (reference bit lines) are individually selectable by the reference-cell selection signals RSA and RSB, no problems occur even with a word line provided to common for the reference cells RefA and RefB.
Referring to FIG. 6, a description will now be made hereunder regarding general routines of the program and verify operations to be performed in the conventional NOR flash memory device constructed as described above.
FIG. 6 is a flowchart showing the program and verify operations to be performed in the NOR flash memory device 1 shown in FIG. 4. Hereinbelow, the verb “program” is defined to refer to executing processing that increases the threshold voltage of the flash cell, which works as a “storage cell,” by storing electrons in the floating gate of the main cell 14.
First, in step S1, the program control circuit 11 outputs a verify execution signal VRFY1 to the word line voltage generator 12. The word line voltage generator 12, in turn, outputs a verify voltage (of about 5 volts (V)) to the main array row decoder 13 and the reference cell row decoder 15. Then, the main array row decoder 13 and reference cell row decoder 15 set the individual word line voltages of the main cell 14 and the reference cell RefA to the verify voltage (of about 5V).
At step S2, the processing executes a verify operation. The sense amplifier S/A compares the values of currents flowing to two input terminals thereof. Thereby, the sense amplifier S/A compares the threshold voltage of the main cell 14 and the threshold voltage Vtmin of the reference cell RefA, and outputs the comparison result (verify determination signal VRFY2) to the program control circuit 11. In response to the signal VRFY2, the program control circuit 11 determines whether the threshold voltage of the main cell 14 is higher than or equal to the threshold voltage Vtmin of the reference cell RefA.
In step S2, if the threshold voltage of the main cell 14 is determined to be higher than or equal to the threshold voltage Vtmin of the reference cell RefA (if the answer is “Yes”), the processing jumps to the process of step S3. In step S3, the processing determines whether the threshold voltage of the main cell 14 is lower than or equal to the threshold voltage Vtmax of the reference cell RefB. If in step S2 the threshold voltage of the main cell 14 is higher than or equal to the threshold voltage Vtmin of the reference cell RefA and, concurrently, in step S3 the threshold voltage of the main cell 14 is lower than or equal to the threshold voltage Vtmax of the reference cell RefB (if the answer is “Yes”), the processing executes a normal program termination (completes the program). However, if in step S2 the threshold voltage of the main cell 14 is higher than or equal to the threshold voltage Vtmin of the reference cell RefA and, concurrently, in step S3 the threshold voltage of the main cell 14 is not lower than or equal to the threshold voltage Vtmax of the reference cell RefB (if the answer is “No”), the processing executes a forced program termination in step S5 (causes the processing to fail).
In contrast, if in step S2 the threshold voltage of the main cell 14 is not higher than or equal to the threshold voltage Vtmin of the reference cell RefA (if the answer is “No”), the processing proceeds to the subsequent process of step S6. In step S6, the program control circuit 11 outputs a program execution signal PROG to the word line voltage generator 12. In turn, the word line voltage generator 12 outputs a programming voltage (of about 6 to 10 V) to the main array row decoder 13, and the main array row decoder 13 sets the word line voltage of the main cell 14 to the programming voltage (of about 6 to 10 V). In the flash memory, since the threshold voltage of the flash cell (main cell 14) is determined in accordance with the word line voltage for programming, the threshold voltage desired to be set has to be altered.
Subsequently, at step S7, a program pulse voltage, of, for example, 5 V to 6V, is applied from the program circuit 18 only for a 0.5 to 1 μs. (program time) to the drain of the floating-gate transistor of the main cell 14.
At step S8, the word line voltage is altered from the programming voltage (of about 6 to 10 V) to a verify voltage (of about 5 V).
At step S9, a verify operation is executed to determine whether the threshold voltage of the flash cell (main cell 14) is higher than or equal to the threshold voltage Vtmin of the reference cell RefA. If at step S9 the threshold voltage is higher than or equal to the threshold voltage Vtmin (if the answer is “Yes”), the processing determines at the subsequent step S4 whether the threshold voltage of the flash cell is lower than or equal to the threshold voltage Vtmax. If at step S9 the threshold value is higher than or equal to the threshold voltage Vtmin, and concurrently if at step S3 the threshold voltage is lower than or equal to the threshold voltage Vtmax (if the answer is “Yes”), the processing goes to step S4 to execute a normal program termination (completes the program processing). On the other hand, if at step S9 the threshold voltage of the flash cell is higher than or equal to the threshold voltage Vtmin, and concurrently if at step S3 the threshold voltage is not lower than or equal to the threshold voltage Vtmax (if the answer is “No”), the processing proceeds to step S5 to execute a force program termination process (causes program failure).
In contrast, if at step S9 a verify operation is executed and the threshold value of the flash cell (main cell 14) is determined to be not higher than or equal to the threshold voltage Vtmin (if the answer is “No”), at step S10 the processing counts the number of executions (execution counts) of the program-pulse application routine. If the count value is less than the value of a preset maximum set count (if the answer is “Yes”), the processing returns to the process of step S6 to reperform a program-pulse application process. On the other hand, if the count value has reached the value of the preset maximum set count (if the answer is “No”), the processing executes a forced program termination process (causes program failure) to prevent the program routine from entering an endless loop at step S5.
In the processes of the individual steps, no problems occur even without steps S1 and S2 being carried out in the case of a binary memory. However, in the case of a multi-level memory, the steps S1 and S2 are indispensable to prevent a state variation from being caused by over-programming. In addition, with a binary memory, the processing need not be performed in step S3 to determine whether the threshold voltage of the flash cell is lower than or equal to threshold voltage Vtmax. In addition, as described above, the processing of step S10 is performed to prevent the program routine to enter an endless loop when the selected main cell 14 cannot be programmed or cannot easily be programmed for some reasons.
In the conventional NOR flash memory, the word line voltage is altered corresponding to the state of memory operation at the times of the program pulse application and the program verify execution. This requires voltage control to be performed by providing the word line voltage generator 12 to alter the word line voltage corresponding to the memory operation state.
The voltage control is particularly complex in the case of a multi-level memory. In the case of a flash memory, a high voltage of 6 to 10 V is used for the word line voltage. When such a high voltage is altered, a long time (several hundred ns to several μs) is required after the voltage starts transition until it becomes stabilized. Consequently, problems arise in that the circuit area needs to be increased to meet the circuit size, and delay takes place in time of the program operation. Especially, in the case of a multi-level memory, these problems become more conspicuous as the per-cell information volume increases.